1. Field of the Invention
The present invention relates generally to the art of integrated circuits, and more particularly, to the design of integrated circuits.
2. Description of the Relevant Art
Today's integrated circuits are complex. Computer aided design and computer aided engineering tools are essential in designing these complicated integrated circuits. In the design process, computer aided design and computer aided engineering tools are often used to generate netlist and schematic representations of a complicated integrated circuit. A netlist is a text file describing the integrated circuit. A netlist representation can be translated into a schematic representation and vice versa. Schematics often consist of cells interconnected by nets that collectively and visually demonstrate the functional design of the integrated circuit. Cells represent circuits consisting of elemental elements such as transistors and resistors. Cells may also represent higher level abstractions of circuits including NAND gates, NOR gates, flip flops, etc. Nets represent interconnections that electrically couple cells to one another.
One of the primary goals behind designing complex integrated circuits is to reduce the physical area on a silicon substrate occupied by the integrated circuit. A reduction in integrated circuit area translates into higher production yield which in turn improves product profitability. In pursuit of this goal, it is common industry practice to combine related circuits or gates into a single standard cell. This concept is best explained with reference to an example.
FIG. 1A shows a cell 11 containing a NAND gate 12 and a cell 13 containing an inverter 14. Cells 11 and 13 are coupled together via a net. Cells 11 and 13 may be part of an integrated circuit schematic designed using computer aided design or computer aided engineering tools. The cells are related in that the output of cell 11 is coupled to the input of cell 14. FIG. 1B is a transistor level schematic diagram of gates 12 and 14 of the cells shown in FIG. 1A. FIG. 1C is a semiconductor layout schematic diagram of gates 12 and 14 of the cells shown in FIGS. 1A and 1B.
In FIG. 1C, NAND gate 12 includes a diffusion layer 20 coupled to a metal layer 22 via contacts 24. Inverter 14 also includes a diffusion layer 26 coupled to metal layer 22 via contact 30. Metal layer 22 is typically coupled to a positive voltage source V.sub.DD.
NAND gate 12 includes input pins A and B for receiving input signals. These input pins are coupled to polygates 32 and 34, respectively, via contacts 36 and 40, respectively. Inverter gate 14 includes an input pin 42 coupled to polygate 44 via contact 46.
NAND gate 12 includes diffusion layer 50 coupled to metalization layer 52 via contact 54. Inverter gate 14 likewise includes a diffusion layer 56 coupled to metalization layer 52 via contact 60. Typically, metalization layer 52 is coupled to ground.
The output of NAND gate 12 is represented by pins 62 and 64 coupled to diffusion layers 20 and 50, respectively, by contacts 66 and 70, respectively. Pins 62 and 64 are electrically coupled via metal layer 72. The output of inverter 14 is represented by pin Y coupled to diffusion layers 26 and 56, respectively, via metal layer 76 and contacts 80 and 82. As seen in FIG. 1C, the output of NAND gate 12 is coupled to the input of inverter 14 via metalization line 86.
FIG. 2A shows a logic level schematic diagram of a cell 90 comprising the NAND and inverter gates 12 and 14 of FIG. 1A. FIG. 1B shows a semiconductor layout representation of the cell 90 shown in FIG. 2A. The cell 90 in FIG. 2B includes diffusion layer 92 coupled to metal layer 94 via a pair of contacts 96 and 100. Typically, metal layer 94 is coupled to a positive voltage source V.sub.DD. Cell 90 in FIG. 2B also includes a second diffusion layer 102 coupled to a metal layer 104 via contact 106. Typically, the second metal layer 104 is coupled to ground. Input pins A and B are coupled to polygates 110 and 112, respectively, via contacts 114 and 116, respectively. Output pin Y is coupled to diffusion layers 92 and 102 via metal line 120 and contacts 122 and 124. Internally, metal line 126 couples the output of NAND gate 12 to the input of inverter 14. More particularly, the output of NAND gate 12 includes metal line 130 coupled to diffusion layers 92 and 102 by contact 132 and 134, respectively. The input to inverter gate 14 is defined by metal bond pin 136 coupled to polygate 140 via contact 142.
FIGS. 1C and 2B are similar in structure. The primary difference lies in the shared diffusion layers and diffusion contacts. More particularly, the inverter gate 14 in FIG. 1C includes separate diffusion layers 26 and 56 coupled to metal layers 22 and 52, respectively, via contacts 30 and 60, respectively. Diffusion layers 26 and 56 are separate from the diffusion layers of the NAND gate 12. In contrast, inverter 14 in FIG. 2B shares diffusion layers 92 and 102 in addition to diffusion contacts 100 and 106 with NAND gate 12. This sharing reduces the overall width of cell 90 when compared to the semiconductor layout representation shown in FIG. 1C. Because diffusion to diffusion spacing is typically large with respect to the size of transistors, by sharing diffusion contacts between two adjacent transistors, a significant space saving is realized as can be seen when comparing FIGs. 1C and 2B.